For one of my Computer Engineering classes, I worked with a lab partner to create three versions of a CPU. We started with a MIPS Single Cycle processor and later modified it to create a Pipelined processor. Our first version of the Pipelined processor did not have any hazard detection hardware or data forwarding hardware. This means that any code ran on the processor would have to be meticulously written to avoid any data hazards.

Our second version of the processor did have a hazard detection unit and turned out to be our fastest and most efficient CPU. Amongst other algorithms, we ran a BubbleSort operation on each of the processors and used that as our benchmark for efficiency.  The first picture below is a schematic of our Single-Cycle Processor. The second picture is the Pipelined Processor with hazard detection and data forwarding. My role in this project was using VHDL to create components and connect them. We also used ModelSim to analyze waveforms that our CPU output. Screen Shot 2019-05-02 at 7.46.47 PM

Screen Shot 2019-05-02 at 7.47.01 PM